1. Technical Field
The present invention relates to a semiconductor memory apparatus, and in particular, to a power supply circuit for a bit-line sense amplifier of a semiconductor memory apparatus.
2. Related Art
As semiconductor related technologies are developed, the number of memory cells in semiconductor memory apparatuses increases. Therefore, when manufacturing semiconductor memory apparatuses, by making a unit cell that is capable of storing data have the smallest possible size within technical limitations, large numbers of unit cells can be integrated in one semiconductor memory apparatus. Thus, since the unit cell is minutely designed so as to have a size of submicron or less, the size of a signal corresponding to data that is stored in one minute unit cell is very small. Meanwhile, in order to read the data that is stored in the memory cell of the semiconductor memory apparatus, an operation of detecting and amplifying the data in the unit cell is inevitably necessary. A sense amplifier is a circuit for detecting and amplifying the data in the unit cell.
Further, there has been a demand for low power consumption of the semiconductor memory apparatus. For this demand, the amount of a power supply voltage used for operating the semiconductor memory apparatus is reduced. Further, recently, a semiconductor memory apparatus that is capable of operating at a power supply voltage of 1.5 V or less has been developed. However, even though the power consumption is reduced due to the reduced potential of the power supply voltage of the semiconductor memory apparatus, there is a problem in that an operational timing for inputting and outputting data is increased.
Some ideas for satisfying the requirements such as low power consumption and reduced data input/output timing are applied to the semiconductor memory apparatus, and one of them relates to an over driving operation.
The over driving operation refers to a method of reducing or optimizing the operational timing by temporarily applying a voltage having a higher level than an internal voltage level that is required for actual operation. According to the over driving operation, by temporarily increasing the driving voltage level of the sense amplifier at an initial step in which the sense amplifier detects and amplifies the data of the unit cell, the sense amplifier can quickly detect and amplify the data.
For this reason, a circuit that supplies the driving voltage to the sense amplifier must supply different voltage at every timing.
FIG. 1 is a block diagram schematically showing a structure of a sense amplifier of a typical semiconductor memory apparatus.
Referring to FIG. 1, a semiconductor memory apparatus generally includes a cell region 10 in which a plurality of unit cells are arranged; a bit-line sense amplifier unit 20 in which a plurality of sense amplifiers are arranged to detect and amplify data signals stored in the unit cells of the cell region 10; a data input/output unit 40 that outputs data signal amplified by the bit-line sense amplifier unit 20; and a sense amplifier voltage supply unit 30 that supplies a driving voltage to the bit-line sense amplifier unit 20.
In the cell region 10, the plurality of unit cells are arranged in an array, and a data signal of the unit cell that is selected so as to correspond to an input address is detected and amplified by the bit-line sense amplifier unit 20, and then transferred to the data input/output unit 40 to be output. In this case, the driving voltage for driving the bit-line sense amplifier unit 20 is supplied from the sense amplifier voltage supply unit 30.
FIG. 2 is a block diagram showing a sense amplifier circuit according to the related art.
Referring to FIG. 2, as described above, the semiconductor memory apparatus according to the related art includes a cell region 10 having a plurality of unit cells, a sense amplifier unit 21 for detecting and amplifying data signals stored in the unit cells, and a sense amplifier voltage supply unit 30 for supplying driving voltages RTO and SB to the sense amplifier 21. Even though the bit-line sense amplifier unit 20 shown in FIG. 1 includes a plurality of sense amplifiers, only one sense amplifier 21 is shown in FIG. 2 for the sake of convenience.
First, the driving voltages RTO and SB are supplied from the sense amplifier voltage supply unit 30 to the bit-line sense amplifier 21 to drive the bit-line sense amplifier 21. The driving voltage RTO has a voltage level corresponding to a power supply voltage, and the driving voltage SB has a voltage level corresponding to a ground voltage.
As such, when an address is input, a unit cell that corresponds to the address information is selected (for example, a unit cell 11 is selected) and the data signal stored in the selected unit cell 11 is supplied to a bit line BL.
Then, the bit-line sense amplifier 21 detects a signal difference between the bit line BL to which a data signal is supplied and a bit line bar/BL to which no data signal is supplied and amplifies the bit line pair BL and /BL to have a high level and a low level, respectively, in response to the detected result.
However, as mentioned above, since the level of the power supply voltage of the semiconductor memory apparatus is decreasing, the driving voltage RTO is decreased in correspondence to the decrease of the level of the power supply voltage. Therefore it takes a large amount of time for the bit-line sense amplifier 21 to amplify the bit-line pair BL and /BL to have a high level and a low level. That is, there is a problem in that the voltage difference between the bit-line pair is reduced due to the decreased level of power supply voltage, and thus it takes a large amount of time to detect and amplify the voltage difference.
In order to solve the above problem, by applying the above-mentioned over driving method, at an initial step of detecting and amplifying the signal difference between the bit line pair BL and /BL, a high level of voltage is supplied from the sense amplifier voltage supply unit 30 as a driving voltage RTO, and at the following step thereof, the driving voltage RTO is returned to a voltage level that is normally used when the sense amplifier is driven.
Generally, as the high level of driving voltage RTO, an external power supply voltage VDD that is input to the semiconductor memory apparatus or a power supply voltage Vperi of a peripheral circuit of the semiconductor memory apparatus is used. The power supply voltage of the peripheral circuit is supplied to a peripheral region such as an input/output buffer or a decoder. A core voltage VCORE that is used in an inner core region of the semiconductor memory apparatus is used as a voltage level of a reduced driving voltage RTO. The core voltage VCORE is a voltage maintained at a lower voltage level than the power supply voltage VDD by a predetermined level and is used to drive the core region of the semiconductor memory apparatus.
Therefore, since a voltage that is higher than a normal driving voltage level is used during an initial step, that is, an overdriving period when the bit-line sense amplifier detects and amplifies the voltage difference between the bit-line pair BL and /BL, an addition circuit is needed to return to the original driving voltage level after the over driving period.
The sense amplifier voltage supply unit 30 supplies a high level bit-line sense amplifier driving voltage RTO during the over driving period, and discharges the original bit-line sense amplifier driving voltage RTO to a predetermined level so as to be applied to the bit-line sense amplifier.
That is, the semiconductor memory apparatus according to the related art discharges the elevated level of the bit-line sense amplifier driving voltage RTO during a selective timing by the sense amplifier voltage supply unit 30.
However, the level of the power supply voltage or the core voltage of the semiconductor memory apparatus may be varied due to noise. Also, when the level of the power supply voltage and the core voltage are changed depending on a type of the applied system, the detecting process or the amplifying process of the bit-line sense amplifier may not be smoothly performed due to the operation that discharges the elevated level of the bit-line sense amplifier driving voltage RTO during the selective timing.
Further, when the level of the bit-line sense amplifier driving voltage RTO is significantly over discharged, an error may occur in the following operating of the bit-line sense amplifier after the over driving operation.